1、<p><b>　　中文3730字</b></p><p>　　智能小車控制中模糊-PID控制的實(shí)現(xiàn)</p><p>　　摘要：本文設(shè)計(jì)了一個(gè)自動(dòng)智能小車控制系統(tǒng)和模糊-PID控制算法。 提出了一個(gè)設(shè)計(jì)模糊PID控制器的方案。通過matlab的仿真分析表明,模糊- PID控制算法的性能比一般的PID控制更好。智能小車的試驗(yàn)結(jié)果表明它會(huì)隨黑色的引導(dǎo)線快速并且穩(wěn)

2、定的走完整個(gè)行程。</p><p>　　關(guān)鍵詞：模糊PID；智能小車；模糊控制器；模糊控制。 </p><p><b>　　1．簡(jiǎn)介</b></p><p>　　近年來(lái),許多國(guó)家正在研制無(wú)人駕駛的車輛技術(shù)。產(chǎn)生了許多新的理論和應(yīng)用技術(shù)。文獻(xiàn)[1]中提出了一個(gè)采用實(shí)時(shí)檢測(cè)速度從而準(zhǔn)確、動(dòng)態(tài)改變小車轉(zhuǎn)向的理論，從而實(shí)現(xiàn)轉(zhuǎn)向完美特性的控制策略。文獻(xiàn)[

3、2]中采用邊緣檢測(cè)算法來(lái)提取道路信息，并采用了比例控制。文獻(xiàn)[3]提出了一種有效、具有良好抗干擾性的、適應(yīng)性強(qiáng)的動(dòng)態(tài)圖像處理算法。這種算法有效的解決了由環(huán)境光線變化以及軌道變化所引起的小車偏離軌道現(xiàn)象。文獻(xiàn)[4]利用非線性最優(yōu)化重建了軌道和攝像調(diào)整間的空間關(guān)系，從而使它能夠精確的測(cè)量出橫向偏差。上述方案都從某種意義上改善了小車的性能，但他們都缺少以小車運(yùn)動(dòng)和大量實(shí)驗(yàn)為基礎(chǔ)的小車的特性。這篇文章中提出了一個(gè)模糊控制算法以及模糊PID控制器

4、的設(shè)計(jì)方法。在本文最后,給出了實(shí)驗(yàn)結(jié)果來(lái)證明模糊PID算法的有效性。</p><p><b>　　2．硬件系統(tǒng)設(shè)計(jì)</b></p><p>　　要實(shí)現(xiàn)模糊PID控制算法的設(shè)計(jì)，有必要設(shè)計(jì)一個(gè)智能小車硬件系統(tǒng)。智能小車應(yīng)該有由道路檢測(cè)，轉(zhuǎn)角檢測(cè)，速度檢測(cè)等構(gòu)成的智能控制單元。詳見圖1。</p><p>　　圖1 智能小車原理框圖</p>

5、;<p>　　3．模糊PID控制的基本原則</p><p>　　用一般的PID控制算法來(lái)獲得最好的響應(yīng)是不容易的。因?yàn)閰?shù)Kp、Ki、Kd不適應(yīng)于不同的對(duì)象，或者同一個(gè)對(duì)象的不同狀態(tài)。模糊控制是以模糊集合和模糊邏輯為機(jī)車的。不需要精確的數(shù)學(xué)模型，它可以由用經(jīng)驗(yàn)建立起來(lái)的規(guī)則表來(lái)確定控制變量的大小。一般來(lái)說，模糊控制的輸入變量基于系統(tǒng)的誤差E和系統(tǒng)的誤差變化量Ec。這和比例－微分控制相似。這樣的控制可

6、能可以獲得較好的動(dòng)態(tài)性能，但獲得的靜態(tài)性能不能讓人滿意。</p><p>　　將模糊控制于PID控制結(jié)合起來(lái)，這就會(huì)使系統(tǒng)即具有模糊控制所具有的靈活的適應(yīng)特性，又具有PID控制的所具有的較高的精確度。圖2給出了模糊PID控制系統(tǒng)的結(jié)構(gòu)圖，其中模糊控制器的作用是選擇不同的PID參數(shù)來(lái)改善局部響應(yīng)，進(jìn)而改善整體的響應(yīng)。</p><p>　　圖2 模糊PID控制仿真框圖</p>&

7、lt;p>　　4．模糊PID控制器的設(shè)計(jì)</p><p>　　速度驅(qū)動(dòng)電機(jī)控制器的設(shè)計(jì)和下面給出的轉(zhuǎn)向機(jī)構(gòu)控制器設(shè)計(jì)是相似的。模糊控制器由模糊化、模糊推理、去模糊化組成，這些都是以知識(shí)庫(kù)為基礎(chǔ)的?？刂破鬏斎霝檎`差及誤差變化量，輸出為參數(shù)Kp、Ki、Kd。</p><p>　　假設(shè)誤差E的模糊集合為{NB NM NS NO PO PS PM PB};誤差變化量Ec、參數(shù)Kp、Ki、Kd

8、的模糊集合為{NB NM NS ZO PS PM PB}。他們表示的意義為：NB=負(fù)大、NM=負(fù)中、NS=負(fù)小、NO=負(fù)零、ZO=零、PO=正零、PS=正小、PM=正中、PB=正大。得到模糊變量E、EC、Kp、Ki、Kd的隸屬度函數(shù)曲線如圖3至圖7所示：</p><p>　　圖3 Kp隸屬函數(shù)響應(yīng)曲線</p><p>　　圖4 Ki隸屬函數(shù)響應(yīng)曲線</p><p>

9、　　圖5 Kd隸屬函數(shù)響應(yīng)曲線</p><p>　　圖6 E隸屬函數(shù)響應(yīng)曲線</p><p>　　圖7 Ec隸屬函數(shù)響應(yīng)曲線</p><p>　　在模糊化完成后需要建立規(guī)則表，根據(jù)規(guī)則表的描述，可以總結(jié)出56個(gè)模糊條件語(yǔ)句，形式例如：如果(E 是 PB) 并且 (Ec 是 PB)那么(Kp 是 PB) (Ki 是 ZO) (Kd是 PB)。詳見表1—表3。<

10、/p><p>　　最后一個(gè)步驟是去模糊化和建立查詢表。在模糊控制中查詢表應(yīng)該嵌入到程序中。假設(shè)輸入的值是固定的那么可以在表中查出相應(yīng)的輸出值。實(shí)際上，這可以節(jié)省許多計(jì)算時(shí)間并使控制簡(jiǎn)化。</p><p><b>　　表1 Kp規(guī)則表</b></p><p><b>　　表2 Ki規(guī)則表</b></p><p

11、><b>　　表3 Kd規(guī)則表</b></p><p><b>　　5．實(shí)驗(yàn)結(jié)果分析</b></p><p>　　圖8 PID控制響應(yīng)曲線</p><p>　　圖9 模糊PID控制響應(yīng)曲線</p><p>　　實(shí)驗(yàn)利用了文獻(xiàn)[7]中的轉(zhuǎn)向機(jī)構(gòu)模型，它的仿真回路已經(jīng)由圖2給出。我們已經(jīng)用MATL

12、AB仿真出了一般PID控制算法和模糊PID控制算法，獲得的響應(yīng)曲線如圖8、圖9所示。</p><p>　　實(shí)驗(yàn)結(jié)果表明，同一般得PID控制相比模糊控制的響應(yīng)時(shí)間要短且沒有超調(diào)的。系統(tǒng)的動(dòng)態(tài)性能有了重大的提高。</p><p><b>　　6．總結(jié)和展望</b></p><p>　　這篇文章給出了一個(gè)控制智能小車的設(shè)計(jì)方案，并且通過實(shí)驗(yàn)從實(shí)際上很

13、好的驗(yàn)證了這個(gè)方案。</p><p>　　無(wú)人駕駛智能小車是以計(jì)算機(jī)技術(shù)、模式識(shí)別以及智能控制技術(shù)的發(fā)展為基礎(chǔ)的。許多國(guó)家和機(jī)構(gòu)都在做這一方面的研究，但它是一個(gè)復(fù)雜的系統(tǒng)，它包含了許多方面的技術(shù)，所以任何一個(gè)技術(shù)的發(fā)展都是重要的，這可能成為智能車發(fā)展的瓶頸。</p><p>　　7．S12XS系列裝置概況</p><p><b>　　7．1介紹</b

14、></p><p>　　新的S12XS系列16位微控制器是一個(gè)具兼容性的S12XE系列的簡(jiǎn)化版本。這些系列成員提供了一個(gè)簡(jiǎn)便的途徑來(lái)開發(fā)通用平臺(tái)的低端到高端化應(yīng)用。將軟件和硬件的重新設(shè)計(jì)降到最少。以通用汽車應(yīng)用和CAN節(jié)點(diǎn)應(yīng)用為目的，一些典型的應(yīng)用如： 車身控制器，乘員檢測(cè)，車門模塊，RKE接收器，智能制動(dòng)器，照明模塊和只能接線箱。</p><p>　　S12XS系列保持了S12XE

15、系列的一些特征包括閃存器糾錯(cuò)代碼（EEC），一個(gè)獨(dú)立的用來(lái)存儲(chǔ)代碼和數(shù)據(jù)的數(shù)據(jù)閃存模塊，提高電磁兼容性能的調(diào)頻鎖定環(huán)和一個(gè)快速ATD轉(zhuǎn)換器。S12XS系列在保持了16位微處理器的所有優(yōu)點(diǎn)和效率的同時(shí)保持了低成本低能耗、電磁兼容性和代碼長(zhǎng)度優(yōu)勢(shì)被目前飛思卡爾16位S12和S12X微處理器系列的使用者所喜愛。</p><p>　　同S12X的成員一樣S12XS系列運(yùn)行16為存取，外設(shè)和記憶元件無(wú)需等待狀態(tài)。S12XS

16、可以選擇112引腳薄型四側(cè)封裝，80引腳四列封裝，64引腳薄型四側(cè)封裝進(jìn)行封裝并保持和S12XS系列一樣的高引腳兼容性。除了每個(gè)模塊可用的I/0端口，多達(dá)18個(gè)I/O端口具有中斷能力允許從停止或等待狀態(tài)被喚醒。</p><p>　　外部設(shè)備包括：MSCAN（可擴(kuò)展控制器區(qū)域網(wǎng)絡(luò)），SPI（串行外設(shè)接口），2個(gè)SCI，8通道24位周期中斷時(shí)鐘，8通道16位定時(shí)器，8通道PWM和12通道16位ATD轉(zhuǎn)換器。軟件控制的

17、外設(shè)-端口路由選擇使得以更少的引腳線數(shù)封裝來(lái)靈活混雜的使用外設(shè)模塊成為可能。</p><p><b>　　7．1．1特性</b></p><p>　　S12XS系列的特征都在這里列出，表一列出了內(nèi)存選項(xiàng)的特征，表二列出了外設(shè)特征，這個(gè)外設(shè)特征在其他系列中也是適用的。</p><p><b>　　16位cpu12X</b>&

18、lt;/p><p>　　向上兼容S12指令系統(tǒng)，但是除了已經(jīng)被移除的五個(gè)模糊指令(MEM, WAV, WAVR, REV, REVW）</p><p><b>　　加強(qiáng)了變址尋址</b></p><p>　　獲得大量的數(shù)據(jù)段而不依賴ppage</p><p><b>　　中斷模塊</b></p&

19、gt;<p><b>　　七個(gè)層次嵌套的中斷</b></p><p>　　靈活的分配中斷源到每一個(gè)中斷水平</p><p>　　外部非可屏蔽高優(yōu)先級(jí)中斷</p><p>　　下一個(gè)輸入可以做為喚醒中斷</p><p>　　中斷請(qǐng)求和非可屏蔽中斷請(qǐng)求</p><p><b>

20、　　總線接收引腳</b></p><p><b>　　SCI接受引腳</b></p><p>　　模塊映射控制（MMP）</p><p><b>　　調(diào)試模塊（DBG）</b></p><p>　　64×64位圓形緩沖區(qū)采集流量變化信息或內(nèi)存訪問信息</p>&l

21、t;p>　　后臺(tái)調(diào)試模塊（BDM）</p><p>　　OSC_LCP (oscillator)振蕩器</p><p>　　低功率回路控制皮爾斯振蕩器利用4MHZD到16MHz晶振</p><p><b>　　良好的抗干擾度</b></p><p>　　CRG 時(shí)鐘及復(fù)位發(fā)生器</p><p&g

22、t;<b>　　COP看門狗</b></p><p><b>　　實(shí)施中斷</b></p><p>　　在自同步模式下快速?gòu)耐Ｖ寡b態(tài)被喚醒</p><p><b>　　內(nèi)存選項(xiàng)</b></p><p>　　64K, 128K 和 256K 字節(jié)閃存</p><

23、;p><b>　　閃存的一般特點(diǎn)</b></p><p>　　64個(gè)數(shù)據(jù)位和8個(gè)校驗(yàn)位允許一個(gè)校正位和兩個(gè)檢錯(cuò)位</p><p>　　擦除扇形區(qū)1024位</p><p>　　自動(dòng)化程序和消除算法</p><p>　　保護(hù)體制防止意外的擦除和程序</p><p>　　保護(hù)選項(xiàng)防止越權(quán)存取&l

24、t;/p><p>　　4K和8K字節(jié)數(shù)據(jù)存儲(chǔ)空間</p><p>　　16通道12位模數(shù)轉(zhuǎn)換器</p><p>　　8 / 10 / 12 位分辨率</p><p>　　數(shù)據(jù)結(jié)果向左或向右對(duì)齊</p><p>　　為在停止模式下轉(zhuǎn)換的內(nèi)部振蕩器</p><p><b>　　連續(xù)轉(zhuǎn)換模式&l

25、t;/b></p><p>　　16位模擬輸入通道多路轉(zhuǎn)換器</p><p><b>　　多通道SCANCS</b></p><p>　　引腳可以用來(lái)做數(shù)字量輸入或輸出</p><p>　　MSCAN(可擴(kuò)展控制器區(qū)域網(wǎng)絡(luò))</p><p>　　1Mb每秒，CAN2.0A、B軟件兼容模塊&l

26、t;/p><p><b>　　標(biāo)準(zhǔn)和擴(kuò)充的數(shù)據(jù)幀</b></p><p><b>　　0-8字節(jié)數(shù)據(jù)長(zhǎng)度</b></p><p>　　可編程使位速率至1Mbps</p><p>　　5個(gè)先入先出存儲(chǔ)接收緩沖區(qū)</p><p>　　3個(gè)帶有內(nèi)部?jī)?yōu)先權(quán)的傳輸緩沖區(qū)</p>

27、<p>　　單純接聽模式來(lái)監(jiān)測(cè)CAN總線</p><p>　　通過軟件或自動(dòng)恢復(fù)總線關(guān)閉</p><p>　　傳輸或發(fā)送信息16位時(shí)間標(biāo)示</p><p>　　TIM（標(biāo)準(zhǔn)時(shí)鐘模塊）</p><p>　　輸入捕捉或輸出比較8×16位通道</p><p>　　具有8位精度預(yù)分頻器的16位自振蕩計(jì)數(shù)

28、器</p><p>　　1×16位脈沖存儲(chǔ)器</p><p>　　PIT（周期性中斷定時(shí)器）</p><p>　　升級(jí)至4個(gè)有超時(shí)期的定時(shí)器</p><p>　　超時(shí)期在1—224個(gè)總線時(shí)鐘周期中選擇</p><p>　　升級(jí)至8通道*8位或4通道*16位脈寬調(diào)制器</p><p>　

29、　中間對(duì)齊或左對(duì)齊的輸出</p><p>　　大范圍頻率的可編程時(shí)鐘選擇邏輯</p><p>　　串行外圍接口模塊（SPI）</p><p>　　可配置8位或16位字長(zhǎng)</p><p><b>　　傳輸和接收雙重緩沖</b></p><p><b>　　主導(dǎo)或從屬模式</b>

30、</p><p>　　最高位有效或最低位有效移動(dòng)</p><p>　　串行時(shí)鐘相位和極性的選擇</p><p><b>　　2個(gè)串行通信接口</b></p><p><b>　　全雙工或單線運(yùn)行</b></p><p><b>　　13位波特率選擇</b>

31、;</p><p><b>　　可編程的字符長(zhǎng)度</b></p><p>　　可編程的傳輸和接收極性</p><p>　　中斷檢測(cè)和傳輸碰撞檢測(cè)</p><p><b>　　片上穩(wěn)壓器</b></p><p>　　2個(gè)帶基準(zhǔn)源的并行線性穩(wěn)壓器</p><p

32、>　　帶低壓中斷的低壓檢測(cè)</p><p>　　通電復(fù)位（POR）電路</p><p><b>　　低壓重置（LVR）</b></p><p><b>　　輸入/輸出</b></p><p>　　多達(dá)91個(gè)一般用途的輸入輸出引腳</p><p>　　所有輸出引腳驅(qū)動(dòng)強(qiáng)調(diào)

33、可配置</p><p><b>　　封裝方式的選擇</b></p><p>　　112引腳薄型四側(cè)扁平封裝</p><p>　　80引腳四列扁平封裝</p><p>　　64引腳薄型四側(cè)扁平封裝</p><p><b>　　操作條件</b></p><p&

34、gt;　　大范圍單電源供電電壓，從3.135V至5.5V</p><p>　　最大40MHZ CPU總線頻率</p><p>　　環(huán)境溫度從-40℃至125℃</p><p><b>　　溫度選擇：</b></p><p><b>　　-40℃至 85℃</b></p><p&g

35、t;　　-40℃至 105℃</p><p>　　-40℃ 至 125℃</p><p>　　8．HCS12特點(diǎn)</p><p>　　與MC68HC12是一樣的并且以MC68HC11 CPU 為基礎(chǔ)</p><p><b>　　提供高效的內(nèi)存訪問</b></p><p>　　提供滿足程序需求的內(nèi)

36、存</p><p>　　擴(kuò)展了HC11指令系統(tǒng)</p><p>　　增加了一些新的尋址方式</p><p><b>　　允許外部輔助存儲(chǔ)器</b></p><p>　　下面是HCS12 CPU體系結(jié)構(gòu)的概述，HCS12 CPU與MC68HC12相似并且在許多文獻(xiàn)中被稱為CPU12，另一方面CPU12 向上與MC68HC1

37、1 CPU兼容。MC68HC11 和MC68HC12分別被稱為HC11和HC12。同HC12一樣HCS12 CPU將所有暫存器和外設(shè)編址到一個(gè)獨(dú)立的線性地址空間，提供高效的存儲(chǔ)訪問。由于HCS12系列可尋址1Mb地址空間，分頁(yè)表被用來(lái)訪問64-16K地址。這就為系統(tǒng)設(shè)計(jì)者提供了滿足許多應(yīng)用程序需要的內(nèi)存空間。HCS12 CPU指令系統(tǒng)擴(kuò)充了HC11的數(shù)據(jù)傳送，數(shù)據(jù)操作指令，增強(qiáng)了算數(shù)運(yùn)算，增加了分支和控制邏輯。此外，HCS12模塊還增加

38、了尋址方式，成為了17種尋址方式。盡管許多HCS12系列成員含有對(duì)于采用單一整合式驅(qū)動(dòng)電路的程序來(lái)說是理想的片上閃存和隨機(jī)存取存儲(chǔ)器，用戶還是可以安裝裝置訪問外部存儲(chǔ)器。</p><p><b>　　還有更多特點(diǎn)：</b></p><p>　　HCS12具有和M68HC11/M68HC12相同的程序模型</p><p><b>　　沒

39、有新的寄存器</b></p><p>　　沒有改變中斷保存順序</p><p>　　多路復(fù)用和非多路復(fù)用的外部中斷</p><p>　　HCS12可以重新使用已存在的軟件代碼資源</p><p>　　注意：定時(shí)回路的改變時(shí)因?yàn)橛辛诵碌臅r(shí)鐘頻率、字節(jié)計(jì)數(shù)和指令周期時(shí)間</p><p>　　HCS12在用新的指

40、令時(shí)體現(xiàn)更好的性能</p><p>　　HCS12減少了中斷等待時(shí)間</p><p>　　HCS12提高了運(yùn)算速度</p><p>　　HCS12提高了性能</p><p>　　指令隊(duì)列數(shù)據(jù)提高了性能</p><p>　　在保證準(zhǔn)確性的前提下指令執(zhí)行速度變快了</p><p><b>

41、　　參考文獻(xiàn)</b></p><p>　　[1]魏玉虎、石陳鈺,姜健照張華。基于視覺的智能小車轉(zhuǎn)向控制研究[J].應(yīng)用電子技術(shù),2001(1)。</p><p>　　[2] 李正建,黃麗佳、葛鵬飛,劉翔飛。基于CCD的智能小車自動(dòng)跟蹤系統(tǒng)[J]. 東華大學(xué)學(xué)報(bào)(自然科學(xué)).2008(6)。</p><p>　　[3],張?jiān)浦?，吳成東，施恩一，秦照冰 基于

42、CCD的智能小車導(dǎo)航系統(tǒng)[J].東北大學(xué)學(xué)報(bào)(自然科學(xué)).2009(2)。</p><p>　　[4]李旭章。 基于視覺研究的智能小車橫向偏差測(cè)量方法[J]. 東南大學(xué)雜志(自然科學(xué)版),2007年(1)。</p><p>　　[5]王朋。鋼筋混凝土機(jī)器人的有趣的控制及應(yīng)用[J]. 山東大學(xué).2007。</p><p>　　[6]王磊,王為民。模糊控制理論和應(yīng)用。國(guó)

43、防工業(yè)出版社。1997:19</p><p>　　[7] 魏新。機(jī)電驅(qū)動(dòng)控制系統(tǒng)的設(shè)計(jì)和分析 南京理工大學(xué)2007</p><p><b>　　附英文原文</b></p><p>　　Journal of Measurement Science and Instrumentation Supplement 2010</p><

44、;p>　　Implementation of Fuzzy-PID in Smart Car Control</p><p>　　Abstract—An unmanued smart car control system and the fuzzy-PID control algorithm are produced . A design scheme of fuzzy-PID controller is p

45、ut forward. The simulation analysis from matlab indicated that the dynamic performance of fuzzy-PID control algorithm is better than that of usual PID. Experimental result of smart car show that it can follow the black g

46、uide line well and fast-stable complete running the whole trip.</p><p>　　Keywords — fuzzy-PID; smart car; fuzzy controller; fuzzy control</p><p>　　1 Introduction</p><p>　　In recent

47、years, many countries are developing unmanned vehicle technology. This gives birth to many new theories and applied technology. Reference[1] presents the theory of turn ahead which uses real-time monitoring speed to chan

48、ge the turn-in point dynamically, then it implements the control strategy to achieve a perfect characteristics of steering. Reference[2] uses edge detection algorithm to extract track information and adopt P control. Ref

49、erence[3] proposes a efficient, good anti-jamming </p><p>　　2 Hardware system design</p><p>　　To implement the design of fuzzy-PID algorithm, it’s necessary to design a hardware system of smart

50、car. Smart car would have a smart control unite which contain detection of guide line, steering angle value, speed value and so on. See details in Fig.1.</p><p>　　Fig.1 The functional block diagram of smart

51、car</p><p>　　3 Basic principle of fuzzy-PID</p><p>　　It’s difficult for usual PID control algorithm to achieve the best effect. Because, the parameters Kp, Ki, Kd can’t adjust to different objec

52、t or different state of the same object. Fuzzy control is based on fuzzy set and fuzzy logic. Without precise mathematical model it can determine the size of controlled variable according the rule table organized by expe

53、rience. In general, fuzzy control input variables are based on system error E and error change EC, which is similar to PD control. Such con</p><p>　　Combining fuzzy control and PID control, this would make a

54、 system have both flexibility-adaptablity of fuzzy control and high accuracy of PID control.Fig.2 shows the structure diagram of fuzzy-PID control system, in which fuzzy controller is responsible for selecting a differen

55、t PID parameter to improve the local performance thus increasing over all performance.</p><p>　　4 Design of fuzzy-PID controller</p><p>　　Speed drive motor controller design is similar to the fo

56、llowing example for steering gear controller design. Fuzzy controller consists of fuzzification, fuzzy-inference and defuzzification, which are based on the knowledge base.[6] Controller input error and error change, out

57、put the parameters Kp,Ki,Kd.</p><p>　　Suppose the fuzzy set for E is{NB,NM,NS,NO,PO,PS，PM,PB}; the fuzzy set for EC、 Kp、Ki and Kd is{NB,NM,NS,ZO,PS,PM,PB}. The linguistic meanings are: NB = negative big, NM

58、= negative middle, NS = negative small, NO = negative zero, ZO = zero, PO = positive zero, PS = positive small, PM = positive middle, PB = positive big. So the membership function curves of fuzzy variables E、EC、Kp、Ki and

59、 Kd are shown in the Fig.3-Fig.7:</p><p>　　It’s necessary to establish rule table after finishing fuzzification. According the description of rule table, 56 fuzzy conditional statements can be summed, which

60、look like If (E is PB) and (EC is PB) then (Kp is PB) (Ki is ZO) (Kd is PB). See details in Tab.1-Tab.3.</p><p>　　Then, the last step is defuzzification and making a lookup table. During fuzzy control, the l

61、ookup table would be embed into the program. Suppose input value is fixed, the corresponding output value would be found in the table. Actually, this would save much computing time, and the control would become simply.&l

62、t;/p><p>　　5 Analysis of experimental results</p><p>　　Experiment used the steering gear model provides by reference[7]. The simulation circuit were shown in Fig.2. The usual PID and fuzzy PID algo

63、rithm were all simulinked in the Matlab. Responding curves obtained were shown in Fig.8 and Fig.9. The experimental result show that compared with the usual PID, the responding time of fuzzy-PID algorithm is shorter with

64、out over swing. The system dynamic performance is improved significantly.</p><p>　　6 Conclusion and outlook</p><p>　　This paper provided a design scheme for controlling a smart car, which is pro

65、ved practically and superlatively though experiments. Unmanned smart car is due to the development of computer technology, pattern recognition and intelligent control technique. Many countries and research groups are doi

66、ng research in the area. But it’s a complicated system, which involves a number of technologies. So the development of each technology is important, for it would become the bottleneck of the development </p><p

67、>　　Device Overview S12XS Family</p><p>　　1.1 Introduction</p><p>　　The new S12XS family of 16-bit micro controllers is a compatible, reduced version of the S12XE family. These families provid

68、e an easy approach to develop common platforms from low-end to high-end applications, minimizing the redesign of software and hardware. Targeted at generic automotive applications and CAN nodes, some typical examples of

69、these applications are: Body Controllers, Occupant Detection, Door Modules, RKE Receivers, Smart Actuators, Lighting Modules and Smart Junction Boxes amongs</p><p>　　Families, the S12XS family runs 16-bit wi

70、de accesses without wait states for all peripherals and memories. The S12XS family is available in 112-pin LQFP, 80-pin QFP, 64-pin LQFP package options and maintains a high level of pin compatibility with the S12XE fami

71、ly. </p><p>　　In addition to the I/O ports available in each module, up to 18 further I/O ports are available with interrupt capability allowing Wake-Up from stop or wait modes.</p><p>　　The per

72、ipheral set includes MSCAN, SPI, two SCIs, an 8-channel 24-bit periodic interrupt timer, 8-channel 16-bit Timer, 8-channel PWM and up to 16- channel 12-bit ATD converter. Software controlled peripheral-to-port routing en

73、ables access to a flexible mix of the peripheral modules in the lower pin count package options.</p><p>　　1.1.1 Features</p><p>　　Features of the S12XS Family are listed here. Please see Table D

74、-1 for memory options and Table D-2 for the peripheral features that are available on the different family members.</p><p>　　? 16-bit CPU12X</p><p>　　— Upward compatible with S12 instruction set

75、 with the exception of five Fuzzy instructions</p><p>　　(MEM, WAV, WAVR, REV, REVW) which have been removed</p><p>　　— Enhanced indexed addressing</p><p>　　— Access to large data se

76、gments independent of PPAGE</p><p>　　? INT (interrupt module)</p><p>　　— Seven levels of nested interrupts</p><p>　　— Flexible assignment of interrupt sources to each interrupt leve

77、l.</p><p>　　— External non-maskable high priority interrupt (XIRQ)</p><p>　　— The following inputs can act as Wake-up Interrupts</p><p>　　– IRQ and non-maskable XIRQ</p><

78、p>　　– CAN receive pins</p><p>　　– SCI receive pins</p><p>　　? MMC (module mapping control)</p><p>　　? DBG (debug module)</p><p>　　— 64 x 64-bit circular trace buffer

79、 captures change-of-flow or memory access information</p><p>　　? BDM (background debug mode)</p><p>　　? OSC_LCP (oscillator)</p><p>　　— Low power loop control Pierce oscillator util

80、izing a 4MHz to 16MHz crystal</p><p>　　— Good noise immunity</p><p>　　? CRG (clock and reset generation)</p><p>　　— COP watchdog</p><p>　　— Real time interrupt</p>

81、;<p>　　— Clock monitor</p><p>　　— Fast wake up from STOP in self clock mode</p><p>　　? Memory Options</p><p>　　— 64K, 128K and 256K byte Flash</p><p>　　— Flash G

82、eneral Features</p><p>　　– 64 data bits plus 8 syndrome ECC (Error Correction Code) bits allow single bit failure</p><p>　　correction and double fault detection</p><p>　　– Erase sec

83、tor size 1024 bytes</p><p>　　– Automated program and erase algorithm</p><p>　　– Protection scheme to prevent accidental program or erase</p><p>　　– Security option to prevent unauth

84、orized access</p><p>　　4K and 8K byte Data Flash space</p><p>　　– 16 data bits plus 6 syndrome ECC (Error Correction Code) bits allow single bit failure</p><p>　　correction and doub

85、le fault detection</p><p>　　– Erase sector size 256 bytes</p><p>　　– Automated program and erase algorithm</p><p>　　— 4K, 8K and 12K byte RAM</p><p>　　? 16-channel, 12-

86、bit Analog-to-Digital converter</p><p>　　— 8/10/12 Bit resolution</p><p>　　— Left or right justified result data</p><p>　　— Internal oscillator for conversion in Stop modes</p>

87、;<p>　　— Continuous conversion mode</p><p>　　— Multiplexer for 16 analog input channels</p><p>　　— Multiple channel scans</p><p>　　— Pins can also be used as digital I/O</

88、p><p>　　? MSCAN (1 M bit per second, CAN 2.0 A, B software compatible module)</p><p>　　— 1 M bit per second, CAN 2.0 A, B software compatible module</p><p>　　– Standard and extended da

89、ta frames</p><p>　　– 0 - 8 bytes data length</p><p>　　– Programmable bit rate up to 1 Mbps</p><p>　　— Five receive buffers with FIFO storage scheme</p><p>　　— Three tra

90、nsmit buffers with internal prioritization</p><p>　　— Listen-only mode to monitor CAN bus</p><p>　　— Bus-off recovery by software intervention or automatically</p><p>　　— 16-bit tim

91、e stamp of transmitted/received messages</p><p>　　? TIM (standard timer module)</p><p>　　— 8 x 16-bit channels for input capture or output compare</p><p>　　— 16-bit free-running cou

92、nter with 8-bit precision prescaler</p><p>　　— 1 x 16-bit pulse accumulator</p><p>　　? PIT (periodic interrupt timer)</p><p>　　— Up to four timers with independent time-out periods&

93、lt;/p><p>　　— Time-out periods selectable between 1 and 224 bus clock cycles</p><p>　　? Up to 8 channel x 8-bit or 4 channel x 16-bit Pulse Width Modulator</p><p>　　— Center- or left-a

94、ligned outputs</p><p>　　— Programmable clock select logic with a wide range of frequencies</p><p>　　? Serial Peripheral Interface Module (SPI)</p><p>　　— Configurable for 8 or 16-bi

95、t data size</p><p>　　— Double-buffered transmit and receive</p><p>　　— Master or Slave mode</p><p>　　— MSB-first or LSB-first shifting</p><p>　　— Serial clock phase and

96、 polarity options</p><p>　　? Two Serial Communication Interfaces (SCI)</p><p>　　— Full-duplex or single wire operation</p><p>　　— 13-bit baud rate selection</p><p>　　—

97、Programmable character length</p><p>　　— Programmable polarity for transmitter and receiver</p><p>　　Break detect and transmit collision detect</p><p>　　? On-Chip Voltage Regulator&

98、lt;/p><p>　　— Two parallel, linear voltage regulators with bandgap reference</p><p>　　— Low-voltage detect (LVD) with low-voltage interrupt (LVI)</p><p>　　— Power-on reset (POR) circui

99、t</p><p>　　— Low-voltage reset (LVR)</p><p>　　? Input/Output</p><p>　　Up to 91 general-purpose input/output (I/O) pins</p><p>　　— Configurable drive strength on all out

100、put pins</p><p>　　? Package Options</p><p>　　— 112-pin low-profile quad flat-pack (LQFP)</p><p>　　— 80-pin quad flat-pack (QFP)</p><p>　　— 64-pin low-profile quad flat-

101、pack (LQFP)</p><p>　　? Operating Conditions</p><p>　　— Wide single Supply Voltage range 3.135 V to 5.5 V at full performance</p><p>　　— 40MHz maximum CPU bus frequency</p>&l

102、t;p>　　— Ambient temperature range –40?C to 125?C</p><p>　　— Temperature Options:</p><p>　　– –40?C to 85?C</p><p>　　– –40?C to 105?C</p><p>　　– –40?C to 125?C</p&g

103、t;<p>　　HCS12 Features</p><p>　　? Is identical to the MC68HC12 and based on the MC68HC11 CPU</p><p>　　? Provides efficient memory access</p><p>　　? Provides memory needed to

104、satisfy many applications</p><p>　　? Extends the HC11 instructions</p><p>　　? Has several new addressing modes added</p><p>　　? Accesses additional memories externally</p>&l

105、t;p>　　Here is an overview of the HCS12 CPU architecture. The HCS12 CPU is</p><p>　　identical to the MC68HC12 and is referred to in most documents as CPU12.</p><p>　　Another factor to consider

106、 is that CPU12 is upward compatible with the</p><p>　　MC68HC11 CPU. The MC68HC11 and the MC68HC12 will be referred to as</p><p>　　the HC11 and HC12 respectively in this module.</p><p&

107、gt;　　Like the HC12, the HCS12 CPU maps all registers and peripherals into a</p><p>　　single linear address space, providing efficient memory access. Since the</p><p>　　HCS12 family supports up t

108、o 1 mega byte of address space, a paging</p><p>　　scheme has been implemented to access as many as 64-16K page windows. This provides system designers with the memory needed to satisfy</p><p>　　

109、many applications.</p><p>　　The HCS12 CPU instruction set extends the HC11 instructions for data movement, data manipulation, enhanced arithmetical operation, and</p><p>　　branching and control

110、logic. In addition, the HCS12 model adds several new</p><p>　　addressing modes for a total of sixteen addressing modes. Although most of</p><p>　　the HCS12 family members have on-chip Flash and

111、RAM, which are ideal</p><p>　　for single chip solutions for many applications, the system designer can</p><p>　　configure the device to access additional memories externally.</p><p>

112、;　　More Features</p><p>　　? The HCS12 has an identical programmers model to M68HC11/M68HC12</p><p>　　– No new registers</p><p>　　– No changes in interrupt stacking order</p>

113、<p>　　– Muxed and non-muxed external interfaces</p><p>　　? The HCS12 can reuse existing software source code.</p><p>　　- Note: timing loops change due to new clock frequency, Byte counts an