1、華中科技大學(xué)碩士學(xué)位論文帶串行接口的RAM映射型32×4點(diǎn)LCD驅(qū)動(dòng)與控制芯片設(shè)計(jì)姓名：吳丹申請(qǐng)學(xué)位級(jí)別：碩士專業(yè)：微電子學(xué)與固體電子學(xué)指導(dǎo)教師：劉三清20040429A B S T R A C TFor its low power, mini bulk, ingenious appearance and cheap cost, LCD has been more and more widely used in today ’

2、s instruments and other electric products. Although a more complex driven circuit and a more difficult interface with SCM compared with LED are needed, the design of LCD has developed gradually

3、into a mature level with the rapid development of VLSI technology. LCD’s native attribute determines that each LCD panel is controlled and (or) driven by a special chip. In this paper, the de

4、sign of a serial 128 pattern (32 4), memory mapping and multi-function LCD controller/driver IC is demonstrated. Based on the “Top-to-down” methodology, the hierarchy partition from top behavioral level

5、 to bottom functional blocks had been framed. Meanwhile, the direct schematic design of some subcircuits had also been conducted in reference to other function-like circuits, using the “Bottom-to-up” met

6、hodology. Then, the whole chip simulation and verification were conducted to examine the matching between the design and the requirements of specification. A mixed-signal simulation method was used to conf

7、irm that timing and function of our design met with the initial specification. This paper put emphasis on the whole design of this dot pattern LCD controller/driver chip, especially on the design o

8、f some critical blocks, such as interface block, timing and control block, driver block and analog block. When circuit design and function verification had been finished, the layout design in a specific process and post-

9、layout verification were accomplished subsequently. The design flow adopted in this paper proves to be successful by Belling ( shanghai) 1.2 m CMOS process. This design not only shortens the time-to-mark